The present invention relates to divider circuits for dividing the frequency of an alternating input signal by a desired divide ratio and, more particularly, to a D flip-flop circuit in which the divide ratio of the flip-flop can be inhibited to pass an applied clock signal therethrough without its repetition rate being altered.
D flip-flops are well known to those skilled in the art and have been used in a myriad of applications. Moreover, D flip-flops have been manufactured utilizing conventional integrated injection logic (I.sup.2 L) technology comprising logic gates formed by open collector NPN transistors, as understood. A typical application for a I.sup.2 L D flip-flop is, for instance, as a frequency divider circuit in a counter system wherein the frequency or repetition rate of a fundamental signal is divided down by a fixed divide ratio. Thus, by cascading a number, N, of D flip-flops in a divider chain it is understood that the repetition rate of the fundamental signal will be divided by a ratio equal to 2.sup.N. Hence, a series of three cascaded D flip-flops will divide the frequency of an applied input clocking signal by 8. One application of a divider chain of the type aforementioned may be found in a digital, crystal controlled function such as a digital watch wherein the frequency of the crystal controlled oscillator is divided by the use of D flip-flops to a one hertz output signal.
Another application for D flip-flop divider chains is found in Electronic Telephone Tone Ringer Integrated Circuits such as the MC34012, a Tone Ringer Circuit manufactured by Motorola, Inc. The MC34012 is fabricated using I.sup.2 L technology and uses D flip-flops and a tone generator circuit to produce a warbling output tone that simulates the telephone bell ringer found in conventional telephones. The tone generator circuit includes an oscillator and a pair of D flip-flop divider chains which produce high and low frequency tones as well as the tone warble frequency by dividing the frequency of the oscillator signal by a predetermined divide ratio. Hence the oscillator frequency (F.sub.1) is divided by a first one of the divider chains to a low frequency warble tone (F.sub.W). The warble frequency is then used to enable a second divider chain to produce a second frequency (F.sub.2) tone that is lower in frequency than F.sub.1. The tone ringer signal is produced by supplying the F.sub.1 and F.sub.2 tones at a modulated F.sub.W rate to an amplifier circuit which in turn drives a piezo transducer, as is understood.
Although divider chains of the above described type function quite well to divide an input frequency by a fixed divide ratio, it may be desired to alter the divide ratio without altering the number of flip-flop circuits used. Hence, for instance, it may be desired to allow the user of a tone ringer integrated circuit to vary the frequency of the oscillator externally to the integrated circuit. If, for example, the oscillator frequency is doubled, it may be necessary to double the frequency divide ratio of one or more of the flip-flops in the internal divider chain of the integrated circuit. Presently, there is no way to alter the divide ratio of internal flip-flop circuits of such tone ringer circuits as the MC34012 without making mask changes during the fabrication of the I.sup.2 L flip-flop circuitry.
Thus, a need exists for a D flip-flop circuit that is suitable for fabrication in integrated circuit form in which the divide ratio thereof can be altered after fabrication.